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25AA320A/25LC320A
2.6
Write Status Register Instruction
See Figure 2-7 for the WRSR timing sequence.
( WRSR )
The Write Status Register instruction ( WRSR ) allows the
TABLE 2-3:
ARRAY PROTECTION
user to write to the nonvolatile bits in the STATUS
register as shown in Table 2-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
BP1
0
0
1
1
BP0
0
1
0
1
Array Addresses
Write-Protected
none
upper 1/4
(0C00h-0FFFh)
upper 1/2
(0800h-0FFFh)
all
(0000h-0FFFh)
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
FIGURE 2-7:
CS
WRITE STATUS REGISTER TIMING SEQUENCE ( WRSR )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
Data to STATUS Register
SI
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
High-Impedance
SO
Note:
An internal write cycle (T WC ) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
? 2009 Microchip Technology Inc.
DS21828F-page 11
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